Tampere University, Applied Materials, and European Partners Demonstrate Brain-Inspired Computing with 5-Bit Ferroelectric Capacitors to Slash AI Energy Consumption

As modern AI models grow, standard computer hardware is hitting a limit, often called the 'memory wall,' where it struggles to process data efficiently. In standard computer designs, data must constantly travel back and forth between separate memory and processing units, which creates delays and uses enormous amounts of electricity. In-memory computing addresses this by performing mathematical calculations directly within the memory cells, eliminating unnecessary data transfers. 

"Capacitive in-memory computing is inherently more efficient than resistive counterparts, as the lack of static current flow fundamentally improves energy efficiency. This development of next-generation AI hardware has taken center stage in the semiconductor industry,” observes Sayani Majumdar.  

“By collaborating with industry leaders like Applied Materials Inc., we are accelerating this technology from lab-to-fab, moving past traditional development cycles toward industrial readiness."  

To make in-memory computing practical for complex AI tasks, each memory cell needs to store more than just basic binary data. In this study, published in the journal Nature Microelectronics and Nanoengineering, the team fabricated ten-nanometer-thick hafnium zirconium oxide capacitors (a specialized material for storing electric charge) capable of storing 32 distinct, linearly programmable electrical states, corresponding to 5-bit precision per cell. Unlike memory designs that rely on current flow and suffer from heat loss, these capacitive devices store electrical charge, enabling high-speed computing with minimal energy loss. 

Achieving such high storage density at the nanoscale devices requires advanced material engineering. Working with Picosun Oy – an Applied Materials Company and Applied Materials Inc., the researchers used an industrial cluster tool for atomic layer deposition (ALD) of the entire memory stack under a continuous vacuum. This seamless process integration prevented chemical contamination and oxidation at the material interfaces, resulting in nearly perfect internal material layers, an exceptionally high breakdown voltage, and record polarization levels without the need for initial "wake-up" cycles. 

"Multi-bit storage in nanoscale ferroelectric devices is often limited by material defects and unpredictable state variations. We have developed a perfect balance of material phases in ultrathin Hf_0.5Zr_0.5O₂ through critical engineering, allowing us to achieve very high polarization and 32 reliable, well-separated analog states.", explains the study’s lead author Ella Paasio. 

To evaluate the hardware's practical impact, the team grouped three 5-bit capacitors to store 15-bit numerical values within a hyperdimensional computing framework. Inspired by the human brain, this framework processes complex data using large mathematical vectors that are naturally resilient to hardware noise. When tested on a benchmark spoken letter recognition dataset, the system achieved 92.3 percent accuracy, matching conventional digital systems while requiring 2.3 times less silicon surface area. 

Beyond standard room-temperature benchmarks, the team subjected the ferroelectric capacitors to rigorous stress testing to evaluate their operational robustness in harsh environments. This validation is critical for confirming that the hardware can withstand the demanding conditions required for specialized, high-stakes computing fields. 

"Given that these ferroelectric capacitors maintain their performance down to 4 Kelvin, this technology holds high potential for extreme computing environments, such as supporting quantum computing infrastructure or space exploration, which is currently being studied in the Chips JU project ARCTIC," notes Majumdar. 

The study is a multi-institutional collaboration led by Tampere University alongside researchers from the Technical University of Munich, affiliates of Applied Materials, Inc. (ALD team from Picosun Oy, and  Ginestra™ modeling and simulation team from Applied Materials Italia Srl), and the University of Modena and Reggio Emilia. The research was supported by the European Union's Chips Joint Undertaking through the KDT-ARTIC project, and Business Finland [Project VETURI - Chip Zero, Grant No. 9971_31_2022]. 

Full article is available at https://www.nature.com/articles/s41378-026-01429-4.epdf