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First System-on-Chip developed in a pioneering project between Tampere University and companies

Published on 1.12.2021
Tampere University
Tutkijoita neuvottelupöydän ja suuren näytön äärellä.
The System-on_chip designed in Finland supports the European Union's objective of increasing self-sufficiency in microchip production. Pictured are researchers from the SoC Hub at Tampere University. Photo: Jonne Renvall / Tampere University.
The first System-on-Chip (SoC) developed by the Finnish SoC Hub consortium has now been taped out. Next the project partners will focus on improving the design, automation and performance of the System-on-Chip. The first of the three chips to be developed by the consortium will be ready for deployment in early 2022.

The Finnish SoC Hub has set out to develop the domain of System-on-Chip design at the forefront in Europe and to enhance Finland’s competitive position. The SoC Hub initiative, coordinated by Tampere University and Nokia, was launched last year. The co-creation activities carried out by the partners go well beyond the scope of a conventional research project.

“The System-of-Chip has been developed using the same methods that are used in industrial production, such as design for testability, extensive verification and focusing on system-level integration instead of single modules,” says Ari Kulmala, professor of practice in System-on-Chip design at Tampere University.

According to Kulmala, the chip can also be tested by external stakeholders as it includes a development kit and can be integrated into a wide range of other systems.

One of the key goals of the SoC Hub project is to enable rapid prototyping for new ideas, for example, in IoT, machine learning or 5G and 6G technologies in silicon.

The newly taped out Ballast chip is the first in a series of three chips. The chip will be manufactured by TSMC, the world’s largest manufacturer of semiconductor chips. Imec research institute is TSMC’s partner in the chip manufacturing in Europe.

Järjestelmäpiirin layout-kuva.
The bonding diagram image (on left) shows how the chip IO pads are wired to the package pins. The package is soldered to the printed circuit board. The layout picture (on right) depicts how the functional blocks are physically located into the chip. The IO pads that are bonded to the package pins are shown on the sides.

The chip is manufactured using TSMC’s recent 22nm Ultra Low Leakage process, which is especially well suited for IoT and Edge devices. The Ballast contains several different RISC-V CPU cores, a Digital Signal Processor, an AI accelerator, rich sensor-like interfaces as well as an extension interface to FPGA. A full software stack – including drivers, software development tools and chip debugging support –  has also been implemented. The chip supports both real time operating systems and Linux simultaneously.

“It has been a pleasure to work with the SoC Hub team. They have been extremely fast to develop the chip, and the quality of the work has been top class,” says Bas Dorren, Director of Business Development at imec.IC-link, part of imec (R&D hub for nano and digital technologies).

Another two chips taped out in the next two years

Considering its large size, the chip was created in a very short time. The ambitious goal was achieved thanks to the good team spirit and the expertise and experience of the specialists involved.

“A great deal of work has been done to enable seamless collaboration between the University and company partners. Several early career researchers have participated in designing Ballast and have therefore had the opportunity to apply the knowledge they acquired from their studies in an industrial project,” says Timo Hämäläinen, head of the Computing Sciences Unit at Tampere University.

Besides the development of the System-on-Chip, the first phase of the project was also a major undertaking, involving the building the consortium and the preparation of the necessary software and license agreements. Headed by Tampere University and Nokia, the consortium comprises CoreHW, VLSI Solution, Siru Innovations, TTTEch Flexibilis, Procemex, Wapice and Cargotec as partners.

In the project funded by Business Finland, three System-on-Chips will be taped out by the end of 2023. Use cases for the chips will be planned together with the project consortium.

“Despite having achieved our first goal, we continue moving forward right away. The time to invest in System-on-Chip development is now, not tomorrow,” emphasises Timo Hämäläinen.

Further information

Timo Hämäläinen
tel. +358 40 8490 777
timo.hamalainen [at]

Ari Kulmala
tel. +358 50 4873 263
ari.kulmala [at]