Open University

Tampere

High-level Synthesis, Lectures

<p>Contact information<br>Email: <span class="spamspan"><span class="u">open.studies.tau</span> [at] <span class="d">tuni.fi</span></span><br>Phone: 0294 520 200</p><p>More information concerning Open University studies<br><a href="https://www.tuni.fi/open-university">tuni.fi/open-university</a></p>

Advanced studies

Faculty of Information Technology and Communication Sciences

Data Processing and Information Technology

<p>Apply for Open University studies by using the following links:</p><p></p><ul><li><a href="https://tau-avoin.ilmoittaudu.fi/lobby/?realization=J-otm-4878907c-f544-4bf4-a9eb-b18d052c66d5_2023-tampere-COMPCE320" target="_blank">COMP.CE.320 High-level Synthesis, lectures, Tampere</a></li></ul><p>You can find a link to the Open University Admissions service and application instructions on the <a href="https://www.tuni.fi/en/study-with-us/open-higher-education-studies/open-university/applying-open-university">Applying to Open University studies</a> page.</p><p>Some of the studies require prior studies. For example, studying intermediate studies may require some completed basic studies. These are described on the Information about studies tab of the study unit under prior requirements.</p><p>When you have been admitted to the studies, you must enrol separately via the Sisu information system for the implementation of the unit of study and, for example if set, for a practise group of your choice. You will receive instructions on how to do this by e-mail after you have confirmed your acceptance of the study place by paying the required fee.</p>

English

Hervanta Campus

Contact teaching

<p>Look information at <a href="https://www.tuni.fi/en/study-with-us/open-higher-education-studies/open-university/applying-open-university">Applying to Open University studies</a>.</p>

<h5>Core content</h5><ul><li>Fundamentals of high-level synthesis</li><li>Scheduling of IO and memories</li><li>Sequential and combinational hardware</li><li>Memory architecture</li><li>Hierarchical design</li><li>Example designs</li></ul><h5>Complementary knowledge</h5><ul><li>General coding style, bit-accurate data types, pipelining, unrolling</li><li>Unconditional/conditional IO</li><li>Shift registers, multiplexors, shifters, accumulators, adder trees, lookup tables</li><li>Memory organization, caching</li><li>Sharing arrays, sharing control variables, reconvergence, channels, arbitration, feedback</li><li>FIR filter, FFT examples<br></li></ul>

<h2>Common</h2><h3>Lecture: </h3><p>09.01.2024 14:00 - 16:00, TAU Tietotalo TC161 opetustila (28)<br>16.01.2024 14:00 - 16:00, TAU Tietotalo TC161 opetustila (28)<br>23.01.2024 14:00 - 16:00, TAU Tietotalo TC161 opetustila (28)<br>30.01.2024 14:00 - 16:00, TAU Tietotalo TC161 opetustila (28)<br>06.02.2024 14:00 - 16:00, TAU Tietotalo TC161 opetustila (28)<br>13.02.2024 14:00 - 16:00, TAU Tietotalo TC161 opetustila (28)<br>20.02.2024 14:00 - 16:00, TAU Tietotalo TC161 opetustila (28)<br>05.03.2024 14:00 - 16:00, TAU Tietotalo TC161 opetustila (28)<br>12.03.2024 14:00 - 16:00, TAU Tietotalo TC161 opetustila (28)<br>19.03.2024 14:00 - 16:00, TAU Tietotalo TC161 opetustila (28)<br>26.03.2024 14:00 - 16:00, TAU Tietotalo TC161 opetustila (28)<br>02.04.2024 14:00 - 16:00, TAU Tietotalo TC161 opetustila (28)<br>09.04.2024 14:00 - 16:00, TAU Tietotalo TC161 opetustila (28)<br>16.04.2024 14:00 - 16:00, TAU Tietotalo TC161 opetustila (28)<br>23.04.2024 14:00 - 16:00, TAU Tietotalo TC161 opetustila (28)<br></p><h2>Voluntary</h2><h3>Exercise: </h3><p>24.01.2024 12:00 - 14:00, TAU Tietotalo TC219 FPGA-laboratorio (21)<br>31.01.2024 12:00 - 14:00, TAU Tietotalo TC219 FPGA-laboratorio (21)<br>07.02.2024 12:00 - 14:00, TAU Tietotalo TC219 FPGA-laboratorio (21)<br>14.02.2024 12:00 - 14:00, TAU Tietotalo TC219 FPGA-laboratorio (21)<br>21.02.2024 12:00 - 14:00, TAU Tietotalo TC219 FPGA-laboratorio (21)<br>06.03.2024 12:00 - 14:00, TAU Tietotalo TC219 FPGA-laboratorio (21)<br>13.03.2024 12:00 - 14:00, TAU Tietotalo TC219 FPGA-laboratorio (21)<br>20.03.2024 12:00 - 14:00, TAU Tietotalo TC219 FPGA-laboratorio (21)<br>27.03.2024 12:00 - 14:00, TAU Tietotalo TC219 FPGA-laboratorio (21)<br>03.04.2024 12:00 - 14:00, TAU Tietotalo TC219 FPGA-laboratorio (21)<br>10.04.2024 12:00 - 14:00, TAU Tietotalo TC219 FPGA-laboratorio (21)<br>17.04.2024 12:00 - 14:00, TAU Tietotalo TC219 FPGA-laboratorio (21)<br>24.04.2024 12:00 - 14:00, TAU Tietotalo TC219 FPGA-laboratorio (21)<br></p>

<p>After the course, the student can implement digital systems using C/C&amp;#43;&amp;#43; <br>based high-level synthesis (HLS). The student understands the whole HLS <br>design flow from specification to implementation on FPGA. He/she can <br>write the source code for the design, the test bench for it, and apply <br>various optimizations with the HLS tool. The student will also <br>understand the capabilities and limitations of HLS with respect to <br>traditional RTL design flow.</p>

<h2>Prerequisites</h2>The student should know the basics of digital design and C/C&amp;#43;&amp;#43; programming before attending this course. Knowledge of VHDL/Verilog HDL is also useful, but not mandatory.<br><h5>Prerequisite</h5><ul><li>Code: TIE-02201</li><li>Name: Programming 2: Basics</li><li>ECTS credits: 5</li><li>Mandatory: Mandatory</li><li>Alternativity: C programming</li></ul><br><h5>Prerequisite</h5><ul><li>Code: TIE-02207</li><li>Name: Programming 2: Basics</li><li>ECTS credits: 5</li><li>Mandatory: Mandatory</li><li>Alternativity: C programming</li></ul><br><h5>Prerequisite</h5><ul><li>Code: TIE-50100</li><li>Name: Digital Design</li><li>ECTS credits: 5</li><li>Mandatory: Mandatory</li><li>Alternativity: Digital design</li></ul><br><h5>Prerequisite</h5><ul><li>Code: TIE-50106</li><li>Name: Digital Design</li><li>ECTS credits: 5</li><li>Mandatory: Mandatory</li><li>Alternativity: Digital design</li></ul><br><h5>Prerequisite</h5><ul><li>Code: TIE-50206</li><li>Name: Logic Synthesis</li><li>ECTS credits: 5</li><li>Mandatory: Advisable</li></ul><h2>Compulsory Prerequisites</h2><ul><li>Digital Design, COMP.CE.200, 5 cr</li><li>Digital Design, COMP.CE.200, 5 cr</li></ul><h2>Recommended Prerequisites</h2><ul><li>Logic Synthesis, COMP.CE.240, 5 cr</li><li>Programming 2: Structures, COMP.CS.110, 5 cr</li></ul>

<h5>Material</h5><ul><li>Type: Lecture slides</li><li>Exam material: Yes</li><li>Language: English</li></ul><h5>Material</h5><ul><li>Type: Book</li><li>Name: High-Level Synthesis Blue Book</li><li>Author: Michael Fingeroff</li><li>Exam material: Yes</li><li>ISBN: 978-1450097246</li><li>Language: English</li><li>Info: The book is available in electric format to the students</li></ul>

<p>Lectures and computer exercises<br></p>

High-level Synthesis, Lectures

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High-level Synthesis, Lectures