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Panu Sjövall: Putting High-Level Synthesis on the trial by implementing an HEVC intra encoder on FPGA with it

Tampereen yliopisto
SijaintiKorkeakoulunkatu 1, 33014 Tampere
Tietotalo auditorium TB109
Ajankohta17.3.2023 10.00–14.00
PääsymaksuMaksuton tapahtuma
Ihmishahmo tohtorinhattu päässään, musta siluetti violetin kuultamalla taustalla.
High-Level Synthesis (HLS) is an automated design process that promises to improve productivity over traditional design methods by increasing design abstraction. In his doctoral dissertation, M.Sc Panu Sjövall put this promise to the test and studied the feasibility of HLS in hardware video codec development. HLS was used throughout the whole High Efficiency Video Coding (HEVC) encoder design process, and the presented proof-of-concept system achieved real-time 4K coding speed up to 120 fps.

High-Level Synthesis (HLS) is a way to improve productivity in the hardware design process by moving away from traditional methods that focus on the details of how the design is implemented (called register transfer level or RTL) and instead focusing on what the design should do (called behavioural level).

HLS tools have been around since the 1990s, but only recently has it started being used more widely in industry and academia. The main reason for this slow adoption rate is that in the past, HLS tools did not produce results that were as good as those obtained with more traditional hardware description languages (HDLs). However, recent advancements in HLS tools have closed this quality of results (QoR) gap.

Using HLS throughout the entire encoder design process enhances the coding performance

Panu Sjövall’s doctoral thesis studies the feasibility of using HLS in the development of video codecs, specifically focusing on the High Efficiency Video Coding (HEVC/H265) standard. HEVC is a key technology for many modern media applications because it can produce the same visual quality as the previous standard (AVC/H264) but with half the data.

However, the increased efficiency comes at a cost of increased computational complexity. Therefore, using automated design methodologies like HLS is crucial to minimize the effort required to implement and verify the design. The doctoral thesis proposes using HLS throughout the entire encoder design process, from data-intensive coding tools like intra prediction and discrete transforms to more control-oriented tools like entropy coding.

“Overcoming the complexity of HEVC and customizing its rich features for a real-time HEVC encoder implementation on hardware is not a trivial task, as hardware development has traditionally turned out to be very time-consuming. This thesis shows that HLS is able to boost the development time, provide previously unseen design scalability, and still result in competitive performance and QoR over state-of-the-art hardware implementations,” Sjövall says.

Public defence on Wednesday 17 March

The doctoral dissertation of MSc. Panu Sjövall in the field of computer engineering titled Feasibility Study of High-Level Synthesis ­- Implementation of a Real-Time HEVC Intra Encoder on FPGA will be publicly examined in the Faculty of Information Technology and Communication Sciences at Tietotalo building at 12 o'clock on Friday 17.03.2023. The Opponents will be Associate Professor Maxime Pelcat, INSA Rennes, France and Dr.-Ing Christian Herglotz, Friedrich-Alexander University Erlangen-Nürnberg, Germany. The Custos will be Associate Professor Jarno Vanne from Tampere University.

The doctoral dissertation is available online.

Picture: Jonne Renvall / Tampereen yliopisto