Sakari Lahti
Responsibilities
University Instructor in digital logic and hardware design
Research topics
High-level synthesis on FPGAs
Research unit
Research fields
Computer Engineering
Latest publications
Leveraging Modern C++ in High-level Synthesis
Lahti, S., Rintala, M. & Hämäläinen, T. D., 2023, In: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 42, 4, p. 1123 - 1132Research output: Contribution to journal › Article › Scientific › peer-review
High-Level Synthesis Implementation of an Embedded Real-Time HEVC Intra Encoder on FPGA for Media Applications
Sjövall, P., Lemmetti, A., Vanne, J., Lahti, S. & Hämäläinen, T., 8 Mar 2022, In: ACM Transactions on Design Automation of Electronic Systems. 27, 4, 34 p.Research output: Contribution to journal › Article › Scientific › peer-review
Implementation of a Nonlinear Self-Interference Canceller using High-Level Synthesis
Lahti, S., Hämäläinen, T., Pascual Campo, P., Anttila, L., Valkama, M. & Lampu, V., 21 Oct 2020, 2020 IEEE International Symposium on Circuits and Systems (ISCAS). Sevilla: IEEE, p. 1-5 5 p.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Scientific › peer-review
Are We There Yet? A Study on the State of High-level Synthesis
Lahti, S., Sjövall, P., Vanne, J. & Hämäläinen, T. D., May 2019, In: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 38, 5, p. 898-911Research output: Contribution to journal › Article › Scientific › peer-review
Designing a clock cycle accurate application with high-level synthesis
Lahti, S., Vanne, J. & Hämäläinen, T. D., 2016, Industrial Electronics Society, IECON 2016 - 42nd Annual Conference of the IEEE. IEEEResearch output: Chapter in Book/Report/Conference proceeding › Conference contribution › Scientific › peer-review
Real-scale Product Development on System Design Course
Hämäläinen, T. D., Sjövall, P., Virtanen, J., Lahti, S. & Vanne, J., Sept 2016, Proceedings of the SEFI Annual Conference 2016. European Society for Engineering Education SEFIResearch output: Chapter in Book/Report/Conference proceeding › Conference contribution › Scientific › peer-review
Integration of TTA processor tools to Kactus2 IP-XACT design flow
Matilainen, L., Lahti, S., Esko, O., Salminen, E. & Hämäläinen, T. D., 2012, NORCHIP 2012, 30th Norchip Conference, Copenhagen, Denmark, 12-13 November, 2012. Piscataway, NJ: IEEE, p. 1-6 6 p. (NORCHIP).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Scientific › peer-review
Contrast changes in STM images and relations between different tunneling models
Nieminen, J., Lahti, S., Paavilainen, S. & Morgenstern, K., 2002, In: Physical Review B. 66, 16, p. s. 165421- 1-9 9 p.Research output: Contribution to journal › Article › Scientific › peer-review