Our research group addresses System-on-Chip (SoC) design, toolsand arhitectures. SoCs are the base of digital services and 400 billion USD business, out of which 20 billion only in the field of artificial intelligence. We cover SoC architectures, Intellectual Property (IP) blocks, design methodologies and tools, as well as software for SoC and edge computing. The main applications are video encoding, machine learning and communication algorithms. Wide range of Xilinx and Intel SoC-FPGAs are used in research projects, and we have also capability for ASIC implementations. Our research group is involved in ongoing SoC Hub ecosystem initiative.
Research focus and goals
The key objective is to implement signal processing and other applications in an optimized way for performance, energy consumption and cost. Application optimization, exploration and division to HW/SW, mapping to off-the-self platform or creating a custom platform are the main research tasks. Our key research topics are
- Metadata based System-on-Chip design descriptions and design flows
- Automated HW/SW code generation from models
- High-Level Synthesis (from C to RTL level hardware descriptions)
- SoC architectures and intellectual property blocks
- RISC-V based systems
- Real-time Linux for embedded systems
- HW accelerated cloud architectures for edge computing
- Machine learning algorithm implementation for CPU, GPU, FPGA and edge platforms
We are the developer of Kactus2, which is the most famous open source IEEE 1685 IP-XACT tool. After the first release in 2011, it has become widely used in hundreds of companies. Other examples of our achievements are fiber optics connected FPGAs for unlimited scalable edge acceleration, RISC-V and TTA based SoC design, Machine Learning performance exploration using AirSim, Distributed Data Service and instruction set simulation, as well as Python code acceleration via RUST compilation.
Kactus2 is a toolset for IP-XACT based SoC design and provides packaging, integration and configuration of HW and SW components, plus register design and HDL import and generation.