Mohsin Abbas

I am currently working as an Assistant Professor (Tenure Track), Computer Engineering at the Faculty of Information Technology and Communication Sciences, Tampere University, Finland. 

A brief introduction about my research Mohsin Abbas

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Tampere University trains future System-on-Chip experts through new Chip Implementation course

Primary responsibilities include research and development, teaching, student supervision, student guidance and mentoring, and participation in departmental activities at Tampere University.

• Teaching Responsibility 

  • COMP.CE.510 Chip Implementation (Fall 2025), Tampere University, Finland.

   

• Active PhD Principal Supervision:
  • Tuomas Aaltonen (full-time), Faculty of Information Technology and Communication Sciences, Tampere University, Finland.
  • Mahdi Maqsudi (full-time), Faculty of Information Technology and Communication Sciences, Tampere University, Finland.
  • Samaneh Ammari (part-time), Faculty of Information Technology and Communication Sciences, Tampere University, Finland
• Active PhD Co-Supervision:
  • Yizheng Wu (full-time), Faculty of Information Technology and Communication Sciences, Tampere University, Finland.
  • Bilal Bashir (full-time),  Faculty of Information Technology and Communication Sciences, Tampere University, Finland.

My research focuses on development of high-throughput, low-latency and energy-efficient VLSI architectures for baseband processing systems, specifically channel code decoders. In addition, my curiosity is fueled by topics such as information theory, VLSI Design, Massive MIMO, 5G/6G, Compute-In-Memory (CiM), URLLC, Green Communication and Universal Channel Code decoders. 

• Awards
  • Outstanding Team Award (5G Radio Access and Application Team), Hong Kong Applied
    Science and Technology Research Institute (ASTRI), 2018, Hong Kong.
  • People’s choice of the SENG Three Minute Thesis (3MT) Competition, Hong Kong University of
    Science and Technology (HKUST), April 2016, Hong Kong.
  •  
• Organizing scientific conferences
  • Chaired a special session titled "Digital: Co-Design and Mixed-Mode" at the 2025 IEEE Nordic Circuits and Systems Conference (NorCAS).
  • Organized a special session titled "Novel algorithms and hardware architectures for channel code decoding" at the 2025 Asilomar Conference on Signals, Systems, and Computers, CA, USA.
  • Organized and chaired a special session titled "Unique decoding solutions for next generation wireless networks" at the 2025 IEEE International Workshop on Signal Processing Systems, Hong Kong.
     

• Academic tutor for new international degree students in Embedded Systems and System on Chip (SoC) Design at Tampere University (since Aug. 2025).
• Academic evaluator for international Master’s Programs in Computing Sciences and Electrical Engineering at Tampere University (since Feb, 2025).
• Planning group member for Computing Sciences and Electrical Engineering at Tampere University (Since Feb, 2025).
          
   

• VLSI Design (ASIC/FPGA)
• SoC Design
• Information theory 
• Channel Coding 
• Wireless Communications (5G/6G)
• Massive MIMO
• Compute-In-Memory (CiM)

• Assistant Professor (Tenure Track), September 2024 - present
  • Faculty of Information Technology and Communication Sciences, Tampere University, Tampere, Finland.
• Research Assistant Professor, November 2023 – August 2024
  • Hong Kong University of Science and Technology (HKUST), Hong Kong  
• Postdoctoral Fellow, November 2022 – November 2023
  • Hong Kong University of Science and Technology (HKUST), Hong Kong  
• Postdoctoral Researcher, October  2019 - 30th September  2022
  • McGill University, Montreal, Canada                       
• Lead Engineer (Hong Kong Applied Science and Technology Research Institute  (ASTRI), September  2017 - September  2019
  • Baseband Solutions, Communication Technology Division, Hong Kong                        

Education:

Electronics and Computer Engineering, Doctor of Philosophy (PhD)

• August 2012 – August 2017 (PhD Advisor: Prof. Chi-Ying Tsui)
• Hong Kong University of Science and Technology (HKUST), Hong Kong
• Ph.D. Thesis: Design of low complexity and high throughput baseband processing blocks for 5G wireless communication

Computer Science and Engineering, Master of Science (MSc)

• August 2009 – August 2011 (Msc. Advisor: Prof. Sangju Park)
• Hanyang University, South Korea

Computer Engineering, Bachelor of Science (BSc)

• September 2003 – September 2007
• University of Engineering and Technology, Taxila, Pakistan

Book 

• S. M. Abbas,  Marwan Jalaleddine, Warren J. Gross “Guessing Random Additive Noise Decoding: A Hardware Perspective” , doi: 10.1007/978-3-031-31663-0, ISBN: 978-3-031-31663-0, Springer Cham, Aug. 2023.

Book Chapters

• S. M. Abbas and Chi-Ying Tsui, “Approximate Matrix Inversion for Linear Pre-coders in Massive MIMO” System-on-Chip in the Nanoscale Era – Design, Verification and Reliability. VLSI-SoC 2016. IFIP Advances in Information and Communication Technology, vol 508. Springer, Cham. https://doi.org/10.1007/978-3-319-67104-8_10.

Journal Papers

• Matti Käyrä, Thomas Szymkowiak, Mohamed Soliman, Antti Rautakoura, Antti Nurmi, Kari Hepola, Henri Lunnikivi, Toni Jääskeläinen, Abdesattar Kalache, Petteri Toivanen, Roope Keskinen, Andreas Stergiopoulos, Väinö-Waltteri Granat, Arto Oinonen, Joonas Multanen, Pekka Jääskeläinen, Karri Palovuori, Timo~D. Hämäläinen and, and S. M. Abbas, “Headsail: One-Year Tape-out of a 25~mm$^2$ Linux-Capable RISC-V MPSoC", submitted to IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2025.
• S. M. Abbas, Marwan Jalaleddine, Chi-Ying Tsui, and Warren J. Gross, “Improved step-GRAND: Low Latency Soft-Input Guessing Random Additive Noise Decoding", in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 33, no. 4, pp. 1028-1041, April 2025, doi: 10.1109/TVLSI.2025.3529637
• S. M. Abbas, Marwan Jalaleddine and Warren J. Gross, “List-GRAND: A practical way to achieve Maximum Likelihood Decoding", in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 31, no. 1, pp. 43-54, Jan. 2023, doi: 10.1109/TVLSI.2022.3223692.
• S. M. Abbas,  Thibaud Tonnellier, Furkan Ercan, Marwan Jalaleddine and Warren J. Gross "High-Throughput and Energy-Efficient VLSI Architecture for Ordered Reliability Bits GRAND”, in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2022, doi: 10.1109/TVLSI.2022.3153605.
• S. M. Abbas,  Marwan Jalaleddine and Warren J. Gross, "Hardware Architecture for Guessing Random Additive Noise Decoding Markov Order (GRAND-MO)", Journal of Signal Processing Systems, 2022, doi:10.1007/s11265-022-01775-2.
• S. M. Abbas, Y. Fan, J. Chen and C. Y. Tsui, “High-Throughput and Energy-Efficient Belief Propagation Polar Code Decoder”, in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 25, no. 3, pp. 1098-1111, March 2017.
• Z. Qian, S. M. Abbas and C. Y. Tsui, "FSNoC: A Flit-Level Speedup Scheme for Network on-Chips Using Self-Reconfigurable Bidirectional Channels" in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 23, no. 9, pp. 1854-1867, Sept. 2015.
• S. M. Abbas, S. Lee, S. Baeg, S. Park, "An Efficient Multiple Cell Upsets Tolerant Content-Addressable Memory" IEEE Transactions on Computers, vol.PP, no.99, pp.1,1, doi: 10.1109/TC.2013.90.

Conference Papers

• Mohamed Soliman, Antti Nurmi, and S. M. Abbas, "Reconfigurable Image Acquisition and Processing Subsystem for MPSoCs," 2025 IEEE International Symposium on Circuits and Systems (ISCAS), London, United Kingdom, 2025, pp. 1-5, doi: 10.1109/ISCAS56072.2025.11043609.
• Tuomas Aaltonen, Mikko Valkama and S. M. Abbas, "Revisiting GRAND via High Level Synthesis," 2025 IEEE Workshop on Signal Processing Systems (SiPS), Hong Kong, 2025, pp. 1-5, doi: 10.1109/SiPS66314.2025.11261267.
• Tuomas Aaltonen, Mikko Valkama and S. M. Abbas, "High Level Synthesis Design for Soft-Input GRAND", in the 2025 Asilomar Conference on Signals, Systems, and Computers.
• Petri Sydänmaa, Jaisal Ashraf and S. M. Abbas, "Novel Verification IP (VIP) for AXI4 interconnects employing Universal Verification Methodology (UVM)" accepted in the 2025 IEEE Nordic Circuits and Systems Conference.
• S. M. Abbas, Marwan Jalaleddine, Chi-Ying Tsui and Warren J. Gross " Step-GRAND: A Low Latency Universal Soft-input Decoder", 2023 IEEE Globecom Workshops (GC Wkshps), Kuala Lumpur, Malaysia. Available Online: arXiv:2307.07133.
• S. M. Abbas, Marwan Jalaleddine and Warren J. Gross "GRAND for Rayleigh Fading Channels", 2022 IEEE GLOBECOM Workshops (GC Wkshps), 4–8 December 2022.
• S. M. Abbas, M. Jalaleddine and W. J. Gross, "High-Throughput VLSI Architecture for GRAND Markov Order," 2021 IEEE Workshop on Signal Processing Systems (SiPS), 2021, pp. 158-163, doi: 10.1109/SiPS52927.2021.00036.
• J. Li, S. M. Abbas, T. Tonnellier and W. J. Gross, "Reduced Complexity RPA Decoder for Reed-Muller Codes," 2021 11th International Symposium on Topics in Coding (ISTC), 2021, pp. 1-5, doi: 10.1109/ISTC49272.2021.9594060.
• S. M. Abbas, Thibaud Tonnellier, Furkan Ercan, Marwan Jalaleddine and Warren J. Gross "High-Throughput VLSI Architecture for soft decision decoding with ORBGRAND", 2021 IEEE International Conference on Acoustics, Speech and Signal Processing, 6-11 June 2021, Toronto,  Canada.
• S. M. Abbas, Thibaud Tonnellier, Furkan Ercan, Warren J. Gross "High-Throughput VLSI Architecture for GRAND," 2020 IEEE Workshop on Signal Processing Systems (SiPS), Coimbra, Portugal, 2020, pp. 1-6, doi: 10.1109/SiPS50750.2020.9195254.
• S. M. Abbas, Y. Fan, J. Chen and C. Y. Tsui, “Concatenated LDPC-Polar Codes Decoding Through Belief Propagation” 2017 IEEE International Symposium on Circuits and Systems (ISCAS), Baltimore, MD, 2017, pp. 1-4.
• S. M. Abbas and Chi-Ying Tsui, "Low-latency approximate matrix inversion for high-throughput linear pre-coders in massive MIMO" 2016 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), Tallinn, 2016, pp. 1-5.
• S. M. Abbas, YouZhe Fan, Ji Chen and Chi-Ying Tsui, "Low complexity belief propagation polar code decoder" IEEE Workshop on Signal Processing Systems (SiPS), 2015, Hangzhou, pp. 1-6.
• S. M. Abbas, S. Hassan and Jongwon Yun, "Augmented reality based teaching pendant for industrial robot" International Conference on Control, Automation and Systems (ICCAS), 2012,  pp. 2210-2213.
• S. M. Abbas, Sanghyeon Baeg, Sungju Park “Multiple Cell Upsets tolerant Content Addressable Memory” International Reliability Physics Symposium (IRPS) April 2011, CA USA.

Patents:
– Syed Mohsin Abbas and Chi-Ying Tsui, “Method and Apparatus for Decoding Channel Codes Employing Compute-In-Memory” Patent No. US 20240411675 A1, Publication Date. 12.12.2024.
– Warren J. Gross, Syed Mohsin Abbas, and Thibaud Tonnellier, “Architecture For Guessing Random Additive Noise Decoding (GRAND)” Patent No. US 11381260 B2, Publication Date. 05.07.2022.
– Hing-Mo Lam, Syed Mohsin Abbas, Zhuohan Yang, Zhonghui Zhang, Man-Wai Kwan, Ching-Hong Leung, Kong-Chau Tsang, “Parallel LDPC Decoder” Patent No. US 10826529 B2, publication Date. 03,11,2020.