VLSI Group

tenure track professor Mohsin Abbas with his students

The Very-large-scale integration (VLSI) group specializes in developing energy-efficient and high-throughput VLSI architectures for baseband processing systems, with an emphasis on information theory and channel coding. Furthermore, the VLSI group is also focused on developing novel compute-in-memory (CIM)-based accelerators for AI/ML systems, as well as large-scale Multi-Processor System on Chips (MPSoCs).

Research focus and goals

VLSI architectures
Compute-in-memory (CiM)
System-on-Chip (SoC) design
5G/6G
Channel Coding

Impact

New System-on-Chip design courses at Tampere University prepare students for industry careers - SoC Hub

Zero-Failure: Dr. Syed Mohsin Abbas and Engineering Near-Flawless Reliability for the 6G Era | Tampere University

Play the video on YouTube (opens in a new tab).

Leader

Mohsin Abbas

Assistant Professor, System-on-Chip design methods, tools, and processes

Faculty of Information Technology and Communication Sciences

Tampere University

mohsin.abbas [at] tuni.fi (mohsin[dot]abbas[at]tuni[dot]fi)

Hervanta Campus

https://orcid.org/0000-0002-5719-3654

PhD Supervision

The VLSI group consists of three full-time PhD students as well as seasonal, short-term master's thesis students.

PhD Students:
- Tuomas Aaltonen (full-time), Faculty of Information Technology and Communication Sciences, Tampere University, Finland.
  - Tuomas focuses on developing efficient hardware universal decoding solutions for future wireless networks employing a framework based on High-Level Synthesis (HLS).
- Mahdi Maqsudi (full-time), Faculty of Information Technology and Communication Sciences, Tampere University, Finland.
  - Mahdi is developing Compute-In-Memory (CIM) macros based on SRAM to speed up computationally intensive AI/ML workloads while adhering to stringent latency and energy constraints.
- Samaneh Ammari (part-time), Faculty of Information Technology and Communication Sciences, Tampere University, Finland
  - Samaneh is investigating the application of AI/ML for future wireless networks.
PhD Co-Supervision:
- Yizheng Wu (full-time), Faculty of Information Technology and Communication Sciences, Tampere University, Finland.
- Bilal Bashir (full-time), Faculty of Information Technology and Communication Sciences, Tampere University, Finland.

Here are a few recent works published by members of the VLSI group.

Journal Papers

Matti Käyrä, Thomas Szymkowiak, Mohamed Soliman, Antti Rautakoura, Antti Nurmi, Kari Hepola, Henri Lunnikivi, Toni Jääskeläinen, Abdesattar Kalache, Petteri Toivanen, Roope Keskinen, Andreas Stergiopoulos, Väinö-Waltteri Granat, Arto Oinonen, Joonas Multanen, Pekka Jääskeläinen, Karri Palovuori, Timo D. Hämäläinen, and Syed Mohsin Abbas, “Headsail: One-Year Tape-out of a 25 mm$^2$ Linux-Capable RISC-V MPSoC", in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 34, no. 4, pp. 1291-1302, April 2026, doi: 10.1109/TVLSI.2026.3653630.
Tuomas Aaltonen and Syed Mohsin Abbas "High-Level Synthesis Based Hardware Implementation Framework for GRANDAB Universal Decoder" submitted to 2026 IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Conference Papers

Mohamed Soliman, Antti Nurmi, and Syed Mohsin Abbas, "Reconfigurable Image Acquisition and Processing Subsystem for MPSoCs," 2025 IEEE International Symposium on Circuits and Systems (ISCAS), London, United Kingdom, 2025, pp. 1-5, doi: 10.1109/ISCAS56072.2025.11043609.
Tuomas Aaltonen, Mikko Valkama, and Syed Mohsin Abbas, "Revisiting GRAND via High Level Synthesis," 2025 IEEE Workshop on Signal Processing Systems (SiPS), Hong Kong, 2025, pp. 1-5, doi: 10.1109/SiPS66314.2025.11261267.
Tuomas Aaltonen, Mikko Valkama, and Syed Mohsin Abbas, "High Level Synthesis Design for Soft-Input GRAND," 2025 59th Asilomar Conference on Signals, Systems, and Computers, Pacific Grove, CA, USA, 2025, pp. 1745-1749, doi: 10.1109/IEEECONF67917.2025.11443870.
Petri Sydänmaa, Jaisal Ashraf, and Syed Mohsin Abbas, "Novel Verification IP (VIP) for AXI4 interconnects employing Universal Verification Methodology (UVM)" 2025 IEEE Nordic Circuits and Systems Conference (NorCAS), Riga, Latvia, 2025, pp. 1-6, doi: 10.1109/NorCAS66540.2025.11231284.

Research focus and goals

Impact

Leader

Mohsin Abbas

PhD Supervision

Future Chips

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