Logic Synthesis, 5 op

Ydinsisältö

• Main phases in implementing a digital circuit.
• Basics of VHDL language and how it is synthesized into circuit.
• Component verification and reuse. Principles of HDL simulator.
• Systems with multiple clock signals. Synchronization interfaces.

Täydentävä tietämys

• System realization in FPGA. Introduction to system design.