Course unit, curriculum year 2023–2024
COMP.CE.240
Logic Synthesis, 5 cr
Tampere University
- Description
- Completion options
- Completion option 1
Passed exam and accepted exercise work
Completion of all options is required.
Logic Synthesis (Exam), English
Logic Synthesis (Participation in teaching), English
Type
Participation in teachingLanguage of instruction
EnglishCredits
0 crGrading scale
Pass-FailResponsible organisation
Faculty of Information Technology and Communication Sciences 100 %
Scheduled teaching
Course unit realisation
Logic Synthesis, Lectures
Lectures (English)
11.1.2024 – 31.5.2024
Active in period 3 (1.1.2024–3.3.2024)
Active in period 4 (4.3.2024–31.5.2024)
Practical design methods of digital logic circuits (VHDL language)
Study methods
Learning environments