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Course unit, curriculum year 2020–2021
COMP.530-02
Verification with UVM, 5 cr
Tampere University
- Description
- Completion options
- Completion option 1
Completed exercises and a short presentation on a single UVM concept.
Verification with UVM (Participation in teaching), English
Type
Participation in teachingLanguage of instruction
EnglishCredits
5 crGrading scale
General scale, 0-5Responsible organisation
Computing Sciences Studies 100 %
Scheduled teaching
Course unit realisation
Verification with UVM, Small group teaching
Small group teaching (English)
14.1.2021 – 2.5.2021
Active in period 3 (1.1.2021–7.3.2021)
Active in period 4 (8.3.2021–31.5.2021)
SystemVerilog and UVM are the current standards in SoC verification. On this course, you will implement a UVM environment for a simple subsystem.
Due to the remote teaching recommendation at the university, all teaching is remote. The remote teaching is facilitated in Zoom.
Study methods
Learning material
Learning environments
Common learning events for all
Exercise:Teachers
Exercise:
Teachers
Lecture:Teachers
Lecture:
Teachers