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Course unit, curriculum year 2020–2021
COMP.530-02
Verification with UVM, 5 cr
Tampere University
- Description
- Completion options
Teaching periods
Active in period 3 (1.1.2021–7.3.2021)
Active in period 4 (8.3.2021–31.5.2021)
Course code
COMP.530-02Language of instruction
EnglishAcademic year
2020–2021Level of study
Advanced studiesGrading scale
General scale, 0-5Persons responsible
Responsible teacher:
Arto OinonenResponsible teacher:
Antti RautakouraResponsible organisation
Computing Sciences Studies 100 %
Core content
- Fundamental concepts in SoC verification
- Object-oriented properties of SystemVerilog language
- UVM Environment
- UVM Tests
Complementary knowledge
- UVM on integration level
- Formal verification
- SystemVerilog as design language
Specialist knowledge
- UVM Register Abstraction Layer
- SystemVerilog DPI
Learning outcomes
Prerequisites
Recommended prerequisites
Completion option 1
Completed exercises and a short presentation on a single UVM concept.
Participation in teaching
14.01.2021 – 02.05.2021
Active in period 3 (1.1.2021–7.3.2021)
Active in period 4 (8.3.2021–31.5.2021)