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Course unit, curriculum year 2023–2024
COMP.CE.320

High-level Synthesis, 5 cr

Tampere University
Teaching periods
Active in period 3 (1.1.2024–3.3.2024)
Active in period 4 (4.3.2024–31.5.2024)
Active in period 5 (1.6.2024–31.7.2024)
Course code
COMP.CE.320
Language of instruction
English
Academic years
2021–2022, 2022–2023, 2023–2024
Level of study
Advanced studies
Grading scale
General scale, 0-5
Persons responsible
Responsible teacher:
Sakari Lahti
Responsible organisation
Faculty of Information Technology and Communication Sciences 100 %
Coordinating organisation
Computing Sciences Studies 100 %
Core content
  • Fundamentals of high-level synthesis
  • Scheduling of IO and memories
  • Sequential and combinational hardware
  • Memory architecture
  • Hierarchical design
  • Example designs
Complementary knowledge
  • General coding style, bit-accurate data types, pipelining, unrolling
  • Unconditional/conditional IO
  • Shift registers, multiplexors, shifters, accumulators, adder trees, lookup tables
  • Memory organization, caching
  • Sharing arrays, sharing control variables, reconvergence, channels, arbitration, feedback
  • FIR filter, FFT examples
Learning outcomes
Prerequisites
Compulsory prerequisites
Recommended prerequisites
Further information
Learning material
Equivalences
Studies that include this course
Completion option 1
Passed exam and exercises.
Completion of all options is required.

Participation in teaching

09.01.2024 31.05.2024
Active in period 3 (1.1.2024–3.3.2024)
Active in period 4 (4.3.2024–31.5.2024)

Exam

29.04.2024 09.06.2024
Active in period 4 (4.3.2024–31.5.2024)
Active in period 5 (1.6.2024–31.7.2024)