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Course unit, curriculum year 2022–2023
COMP.CE.240
Logic Synthesis, 5 cr
Tampere University
- Description
- Completion options
Teaching periods
Active in period 3 (1.1.2023–5.3.2023)
Active in period 4 (6.3.2023–31.5.2023)
Active in period 5 (1.6.2023–31.7.2023)
Course code
COMP.CE.240Language of instruction
EnglishAcademic years
2021–2022, 2022–2023, 2023–2024Level of study
Intermediate studiesGrading scale
General scale, 0-5Persons responsible
Responsible teacher:
Sakari LahtiResponsible organisation
Faculty of Information Technology and Communication Sciences 100 %
Coordinating organisation
Computing Sciences Studies 100 %
Core content
- Main phases in implementing a digital circuit.
- Basics of VHDL language and how it is synthesized into circuit.
- Component verification and reuse. Principles of HDL simulator.
- Systems with multiple clock signals. Synchronization interfaces.
Complementary knowledge
- System realization in FPGA. Introduction to system design.
Learning outcomes
Prerequisites
Compulsory prerequisites
Further information
Learning material
Equivalences
Studies that include this course
Completion option 1
Passed exam and accepted exercise work
Completion of all options is required.
Exam
29.05.2023 – 11.06.2023
Active in period 4 (6.3.2023–31.5.2023)
Active in period 5 (1.6.2023–31.7.2023)
01.05.2023 – 14.05.2023
Active in period 4 (6.3.2023–31.5.2023)
15.05.2023 – 28.05.2023
Active in period 4 (6.3.2023–31.5.2023)
Participation in teaching
09.01.2023 – 31.05.2023
Active in period 3 (1.1.2023–5.3.2023)
Active in period 4 (6.3.2023–31.5.2023)