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Course unit, curriculum year 2021–2022
COMP.CE.240

Logic Synthesis, 5 cr

Tampere University
Teaching periods
Active in period 2 (24.10.2021–31.12.2021)
Active in period 3 (1.1.2022–6.3.2022)
Active in period 4 (7.3.2022–15.5.2022)
Course code
COMP.CE.240
Language of instruction
English
Academic years
2021–2022, 2022–2023, 2023–2024
Level of study
Intermediate studies
Grading scale
General scale, 0-5
Persons responsible
Responsible teacher:
Sakari Lahti
Responsible organisation
Faculty of Information Technology and Communication Sciences 100 %
Coordinating organisation
Computing Sciences Studies 100 %
Core content
  • Main phases in implementing a digital circuit.
  • Basics of VHDL language and how it is synthesized into circuit.
  • Component verification and reuse. Principles of HDL simulator.
  • Systems with multiple clock signals. Synchronization interfaces.
Complementary knowledge
  • System realization in FPGA. Introduction to system design.
Learning outcomes
Prerequisites
Compulsory prerequisites
Further information
Learning material
Equivalences
Kokonaisuudet, joihin opintojakso kuuluu
Completion option 1
Passed exam and accepted exercise work
Completion of all options is required.

Exam

28.02.2022 15.03.2022
Active in period 3 (1.1.2022–6.3.2022)
Active in period 4 (7.3.2022–15.5.2022)
16.03.2022 31.03.2022
Active in period 4 (7.3.2022–15.5.2022)
01.04.2022 24.04.2022
Active in period 4 (7.3.2022–15.5.2022)

Participation in teaching

26.10.2021 09.03.2022
Active in period 2 (24.10.2021–31.12.2021)
Active in period 3 (1.1.2022–6.3.2022)
Active in period 4 (7.3.2022–15.5.2022)