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Course unit, curriculum year 2022–2023
COMP.CE.130

Computer Architecture, 5 cr

Tampere University
Teaching periods
Active in period 3 (1.1.2023–5.3.2023)
Course code
COMP.CE.130
Language of instruction
English, Finnish
Academic years
2021–2022, 2022–2023, 2023–2024
Level of study
Intermediate studies
Grading scale
General scale, 0-5
Persons responsible
Responsible teacher:
Matti Haavisto
Responsible organisation
Faculty of Information Technology and Communication Sciences 100 %
Coordinating organisation
Computing Sciences Studies 100 %
Core content

- Processor structure and instruction execution.
- Data path and data path control.
- Data path pipelining.
- Data dependencies, hazards, forwarding, delayed branching.
- Basic concepts and terms related to processor architecture.

- Memory hierarchy and caches. Locality.
- direct-mapped, set-associative and full-associative caches.

Complementary knowledge

- Speculation and prediction of program performance, branch prediction.
- VLIW and superscalar processor.
- Program/instructions disorder excecution, loop unrolling.
- Exceptions at datapath.
- Data dependencies: independence, output dependency.

- Cache control.
- Cache miss handling.
- Cache coherence.
- Cache performance.
- Reliability.

Specialist knowledge


- Data-level parallelism.
- Introduction to multiprocessor systems.
- Vector processor, GPU.

- Virtual memory.
- Address translation and translation-lookaside buffer.

Learning outcomes
Compulsory prerequisites
Further information
Learning material
Equivalences
Studies that include this course
Completion option 1

Participation in teaching

12.01.2023 27.02.2023
Active in period 3 (1.1.2023–5.3.2023)