Open University

Tampere

System-on-Chip Verification, Lectures

<p>Contact information<br>Email: <span class="spamspan"><span class="u">open.studies.tau</span> [at] <span class="d">tuni.fi</span></span><br>Phone: 0294 520 200</p><p>More information concerning Open University studies<br><a href="https://www.tuni.fi/open-university">tuni.fi/open-university</a></p>

Advanced studies

Faculty of Information Technology and Communication Sciences

Data Processing and Information Technology

<p>Apply for Open University studies by using the following links:</p><p><ul><li><a href="https://tau-avoin.ilmoittaudu.fi/lobby/?realization=J-otm-20863519-0115-4ad1-9aea-3fac4669297d_2023-tampere-COMPCE420" target="_blank">COMP.CE.420 System-on-Chip Verification, lectures, Tampere</a></li></ul></p><p>You can find a link to the Open University Admissions service and application instructions on the <a href="https://www.tuni.fi/en/study-with-us/open-higher-education-studies/open-university/applying-open-university">Applying to Open University studies</a> page.</p><p>Some of the studies require prior studies. For example, studying intermediate studies may require some completed basic studies. These are described on the Information about studies tab of the study unit under prior requirements.</p><p>When you have been admitted to the studies, you must enrol separately via the Sisu information system for the implementation of the unit of study and, for example if set, for a practise group of your choice. You will receive instructions on how to do this by e-mail after you have confirmed your acceptance of the study place by paying the required fee.</p>

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Hervanta Campus

Contact teaching

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<h5>Core content</h5><ul><li>Fundamental concepts in SoC verification</li><li>Object-oriented properties of SystemVerilog language</li><li>Universal Verification Methodology (UVM)<br></li></ul><h5>Complementary knowledge</h5><ul><li>UVM on integration level</li><li>Formal verification</li><li>SystemVerilog as design language</li></ul><h5>Specialist knowledge</h5><ul><li>UVM Register Abstraction Layer</li><li>SystemVerilog DPI<br></li></ul><p></p>

<h2>Common</h2><h3>Lecture: </h3><p>08.01.2024 14:00 - 16:00, TAU Tietotalo TB214 opetustila (32)<br>15.01.2024 14:00 - 16:00, TAU Tietotalo TB214 opetustila (32)<br>22.01.2024 14:00 - 16:00, TAU Tietotalo TB214 opetustila (32)<br>29.01.2024 14:00 - 16:00, TAU Tietotalo TB214 opetustila (32)<br>05.02.2024 14:00 - 16:00, TAU Tietotalo TB214 opetustila (32)<br>12.02.2024 14:00 - 16:00, TAU Tietotalo TB214 opetustila (32)<br>19.02.2024 14:00 - 16:00, TAU Tietotalo TB214 opetustila (32)<br>04.03.2024 14:00 - 16:00, TAU Tietotalo TB214 opetustila (32)<br>11.03.2024 14:00 - 16:00, TAU Tietotalo TB214 opetustila (32)<br>18.03.2024 14:00 - 16:00, TAU Tietotalo TB214 opetustila (32)<br>25.03.2024 14:00 - 16:00, TAU Tietotalo TB214 opetustila (32)<br>08.04.2024 14:00 - 16:00, TAU Tietotalo TB214 opetustila (32)<br>15.04.2024 14:00 - 16:00, TAU Tietotalo TB214 opetustila (32)<br>22.04.2024 14:00 - 16:00, TAU Tietotalo TB214 opetustila (32)<br></p><h2>Room booking</h2><h3>Exercise: Voluntary exercise session</h3><p>09.01.2024 14:00 - 16:00, TAU Tietotalo TC219 FPGA-laboratorio (21)<br>11.01.2024 10:00 - 12:00, TAU Tietotalo TC219 FPGA-laboratorio (21)<br>16.01.2024 14:00 - 16:00, TAU Tietotalo TC219 FPGA-laboratorio (21)<br>18.01.2024 10:00 - 12:00, TAU Tietotalo TC219 FPGA-laboratorio (21)<br>23.01.2024 14:00 - 16:00, TAU Tietotalo TC219 FPGA-laboratorio (21)<br>25.01.2024 10:00 - 12:00, TAU Tietotalo TC219 FPGA-laboratorio (21)<br>30.01.2024 14:00 - 16:00, TAU Tietotalo TC219 FPGA-laboratorio (21)<br>01.02.2024 10:00 - 12:00, TAU Tietotalo TC219 FPGA-laboratorio (21)<br>06.02.2024 14:00 - 16:00, TAU Tietotalo TC219 FPGA-laboratorio (21)<br>08.02.2024 10:00 - 12:00, TAU Tietotalo TC219 FPGA-laboratorio (21)<br>13.02.2024 14:00 - 16:00, TAU Tietotalo TC219 FPGA-laboratorio (21)<br>15.02.2024 10:00 - 12:00, TAU Tietotalo TC219 FPGA-laboratorio (21)<br>20.02.2024 14:00 - 16:00, TAU Tietotalo TC219 FPGA-laboratorio (21)<br>22.02.2024 10:00 - 12:00, TAU Tietotalo TC219 FPGA-laboratorio (21)<br>05.03.2024 14:00 - 16:00, TAU Tietotalo TC219 FPGA-laboratorio (21)<br>07.03.2024 10:00 - 12:00, TAU Tietotalo TC219 FPGA-laboratorio (21)<br>12.03.2024 14:00 - 16:00, TAU Tietotalo TC219 FPGA-laboratorio (21)<br>14.03.2024 10:00 - 12:00, TAU Tietotalo TC219 FPGA-laboratorio (21)<br>19.03.2024 14:00 - 16:00, TAU Tietotalo TC219 FPGA-laboratorio (21)<br>21.03.2024 10:00 - 12:00, TAU Tietotalo TC219 FPGA-laboratorio (21)<br>26.03.2024 14:00 - 16:00, TAU Tietotalo TC219 FPGA-laboratorio (21)<br>04.04.2024 10:00 - 12:00, TAU Tietotalo TC219 FPGA-laboratorio (21)<br>09.04.2024 14:00 - 16:00, TAU Tietotalo TC219 FPGA-laboratorio (21)<br>11.04.2024 10:00 - 12:00, TAU Tietotalo TC219 FPGA-laboratorio (21)<br>16.04.2024 14:00 - 16:00, TAU Tietotalo TC219 FPGA-laboratorio (21)<br>18.04.2024 10:00 - 12:00, TAU Tietotalo TC219 FPGA-laboratorio (21)<br>23.04.2024 14:00 - 16:00, TAU Tietotalo TC219 FPGA-laboratorio (21)<br>25.04.2024 10:00 - 12:00, TAU Tietotalo TC219 FPGA-laboratorio (21)<br></p>

<p>After completing the course, students are able to run the verification flow for a single subsystem in a SoC using a modern standard methodology. They understand how to integrate the subsystem verification environment on a higher level. They know the key metrics used for tracking the verification project.&#160;</p>

<h2>Prerequisites</h2><p>Basic knowledge of digital design with VHDL or Verilog is mandatory. Experience of object-oriented programming is recommended.<br></p><h2>Recommended Prerequisites</h2><ul><li>Programming 2: Techniques, COMP.CS.110, 5 cr</li><li>Logic Synthesis, COMP.CE.240, 5 cr</li><li>Digital Design, COMP.CE.200, 5 cr</li></ul>

<h5>Material</h5><ul><li>Type: Lecture slides</li><li>Author: Arto Oinonen<br></li><li>Exam material: Yes</li><li>Language: English</li><li>Info: Available as pdf download in Plussa</li></ul>

System-on-Chip Verification, Lectures

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System-on-Chip Verification, 5 cr

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System-on-Chip Verification, Lectures