Customized Parallel
Computing (CPC) group

This is the home page of the CPC research group of Tampere University. The group's name in Finnish is Räätälöity rinnakkaislaskenta. CPC's main research focus is on design and programming methodologies of customized parallel computing platforms and real time implementations of challenging algorithms.


In addition to publications and theses listed here as academic contributions, CPC has also made major open source contributions in the field of portable and customized heterogeneous computing: The group has created OpenASIP and Portable Computing Language (pocl) which are being used widely as research platforms and even for product use cases. CPC also created the prototype HIPCL translation tool which evolved into chipStar, a portable CUDA/HIP implementation using open standards.


An algorithm domain with extreme computational demands that CPC has been very interested in the past years is real time ray tracing. A separate focus group was formed for finding algorithmic, parallel/heterogeneous implementation and custom hardware solutions for its challenges in 2015. The group's web pages are here.

The CPC group in Fall 2023.

News

November 16th, 2023: BrainTTA presentation in IEEE ICCD 2023

Our Dutch colleague Maarten Molendijk from TU Eindhoven presented a co-authored paper "BrainTTA: A 28.6 TOPS/W Compiler Programmable Transport-Triggered NN SoC" in IEEE ICCD 2023. The publication was a result of successful collaboration work between our CPC group and PARSE/TUE where a programmable TTA/SIMD-based accelerator was designed for ultra low power AI inference on low precision use cases. The design was done using the OpenASIP tools with the design work conducted by Molendijk et al. Read more about it in the preprint. The presentation slides are available here.

November 6th, 2023: New publications added
  • Topi Leppänen, Joonas Multanen, Leevi Leppänen, Pekka Jääskeläinen:
    AFOCL: Portable OpenCL Programming of FPGAs via Automated Built-in Kernel Management
    in IEEE Nordic Circuits and Systems Conference (NorCAS 2023) (download).
  • Niklas Rother, Leonard Mätzner, Pekka Jääskeläinen, Topi Leppänen, Jens Karsten Schleusner, Holger Christoph Blume:
    Synthetic Aperture Radar Algorithms on Transport Triggered Architecture Processors using OpenCL
    International Radar Conference 2023
  • Maarten Molendijk, Floran de Putter, Manil Dev Gomony, Pekka Jääskeläinen and Henk Corporaal:
    BrainTTA: A 28.6 TOPS/W Compiler Programmable Transport-Triggered NN SoC
    IEEE International Conference on Computer Design (ICCD 2023)
  • Panagiotis Mousouliotis, Topi Leppanen, Pekka Jaaskelainen, Nikos Petrellis, Panagiotis Christakos, Georgios Keramidas, Christos Antonopoulos, Nikolaos Voros:
    On the OpenCL Support for Streaming Fixed-Function Accelerators on Embedded SoC FPGAs
    The 19th International Symposium on Applied Reconfigurable Computing (ARC 2023)
November 1st, 2023: AFOCL presentation in NorCAS 2023 conference

Our doctoral researcher Topi Leppänen presented the paper "AFOCL: Portable OpenCL Programming of FPGAs via Automated Built-in Kernel Management" in NorCAS 2023. AFOCL allows FPGA device users to avoid vendor lock-in and separates the roles of software and FPGA engineer. Behind the curtain, the OpenCL implementation automatically selects IPs from a precompiled bitstream database and handles FPGA reconfiguration. Details in the paper.

August 24th, 2023: Final demonstrator video for the CPSoSAware EU project available

Check out the video below of the final demonstrator for the CPSoSAware EU project. The work was a collaboration with the University of Peloponnese. The demonstrator features a nanodrone, which offloads processing to edge resources wirelessly using Pocl-R.

August 8th, 2023: Added a publication from 2022 missing from the web page
  • Topi Leppänen, Atro Lotvonen, Pekka Jääskeläinen:
    "Cross-vendor programming abstraction for diverse heterogeneous platforms"
    in Frontiers in Computer Science, Vol. 4, Oct. 2022 (download).
June 15th, 2023: Two new publications added
  • Topi Leppänen, Atro Lotvonen, Panagiotis Mousouliotis, Joonas Multanen, Georgios Keramidas, Pekka Jääskeläinen:
    "Efficient OpenCL system integration of non-blocking FPGA accelerators"
    in Microprocessors and Microsystems (MICPRO), Vol. 97, Mar. 2023 (download).
  • Alex Hirvonen, Topi Leppänen, Kari Hepola, Joonas Multanen, Joost Hoozemans, Pekka Jääskeläinen:
    "AEX: Automated High-Level Synthesis of Compiler Programmable Co-processors"
    in Journal of Signal Processing Systems (JSPS), Feb. 2023​ (download).
October 17th, 2022: A master's thesis and a new publication added
  • Kari Hepola:
    Generation of Customized RISC-V Implementations
    (2022) (link)
  • Kanishkan Vadivel, Barry de Bruin, Pekka Jääskeläinen, Roel Jordans and Henk Corporaal:
    "Prebypass: Software Register File Bypassing for Reduced Interconnection Architecture"
    in Euromicro Conference on Digital Systems Design (DSD 2022) (download).
September 22nd, 2022: New publications added
  • Jakub Žádník, Markku Mäkitalo, Pekka Jääskeläinen,
    "Pruned Lightweight Encoders for Computer Vision"
    IEEE 24th International Workshop on Multimedia Signal Processing (MMSP 2022) download poster
  • Kari Hepola, Joonas Multanen and Pekka Jääskeläinen:
    "Dual-IS: Instruction Set Modality for Efficient Instruction Level Parallelism"
    in 35th GI/ITG International Conference on Architecture of Computing Systems (ARCS 2022) (download).
  • Kari Hepola, Joonas Multanen and Pekka Jääskeläinen:
    "OpenASIP 2.0: Co-Design Toolset for RISC-V Application-Specific Instruction-Set Processors"
    in 33rd IEEE International Conference on Applicationspecific Systems, Architectures and Processors (ASAP 2022) (download).

(older news here)

Social Media

Follow the CPC group on Twitter/X: https://twitter.com/CustomParComp

Contact Us

Send email to to contact us.