Customized Parallel Computing (CPC) research group

This is the home page of the Customized Parallel Computing (CPC) research group of Tampere University. Group's name in Finnish is Räätälöity rinnakkaislaskenta.

CPC's main research focus is on design and programming methodologies of customized parallel computing platforms and real time implementations of challenging algorithms.

In addition to publications and theses listed here, CPC has also made two major open source contributions: It leads the development of TCE and Portable Computing Language (pocl).

An algorithm domain with extreme computational demands that CPC has been very interested in the past years is real time ray tracing. A separate focus group was formed for finding algorithmic, parallel/heterogeneous implementation and custom hardware solutions for its challenges in 2015. The group's web pages are here.

News and updates

December 23rd, 2021: New publication, an old master's thesis and a new doctoral dissertation added

  • Topi Leppänen, Panagiotis Mousouliotis, Georgios Keramidas, Joonas Multanen, Pekka Jääskeläinen:
    "Unified OpenCL Integration Methodology for FPGA Designs",
    in NorCAS 2021: IEEE Nordic Circuits and Systems Conference (download).
  • Joonas Multanen:
    Hardware Optimizations for Low-Power Processors (December, 2014) (link)
  • Joonas Multanen:
    Energy-Efficient Instruction Streams for Embedded Processors (November, 2021) (link)

November 8th, 2021: Two master's theses added

  • Topi Leppänen:
    Scalability optimizations for multicore soft processors (2021) (link)
  • Jan Solanti:
    Distributed Low Latency Computing With OpenCL: A Scalable Multi-Access Edge Computing Framework (2020) (link)

November 4th, 2021: New publications added

  • Joonas Multanen, Kari Hepola, Asif Ali Khan, Jeronimo Castrillon, Pekka Jääskeläinen:
    "Energy-Efficient Instruction Delivery in Embedded Systems with Domain Wall Memory",
    in IEEE Transactions on Computers (available as early open access) (download).
  • Jan Solanti, Michal Babej, Julius Ikkala, Vinod Kumar Malamal Vadakital, Pekka Jääskeläinen:
    "PoCL-R: A Scalable Low Latency Distributed OpenCL Runtime",
    in SAMOS XXI: Embedded Computer Systems: Architectures, MOdeling, and Simulation (virtual, July 2021) (download).
  • Jakub Zadnik, Markku Mäkitalo, Jussi Iho, Pekka Jääskeläinen:
    "Performance of Texture Compression Algorithms in Low-Latency Computer Vision Tasks",
    in EUVIP 2021: 9th European Workshop on Visual Information Processing (virtual, 23-25 June 2021) (download).
  • Joost Hoozemans, Kati Tervo, Pekka Jääskeläinen, Zaid Al-Ars:
    "Energy Efficient Multistandard Decompressor ASIP",
    in ICCDE 2021: 7th International Conference on Computing and Data Engineering (virtual, January 2021) (download).

December 10th, 2020: New publications and a blog post

New publications in the fall:

  • Joonas Multanen, Kari Hepola, Pekka Jääskeläinen:
    "Programmable Dictionary Code Compression for Instruction Stream Energy Efficiency",
    in ICCD 2020: The 38th IEEE International Conference on Computer Design (virtual, October, 2020) (download).
  • Kati Tervo, Samawat Malik, Topi Leppänen, Pekka Jääskeläinen:
    "TTA-SIMD Soft Core Processors",
    in FPL2020: 30th International Conference on Field-Programmable Logic and Applications (virtual, August-September, 2020) (download).

The instruction stream energy efficiency paper is featured in a recent blog post as well.

August 19th, 2020: New publication added

  • Joonas Multanen, Heikki Kultala, Kati Tervo, Pekka Jääskeläinen:
    "Energy Efficient Low Latency Multi-issue Cores for Intelligent Always-On IoT Applications",
    in Journal of Signal Processing Systems (2020) (download).

June 16th, 2020: Three old master's theses added

For some reason, there were three extremely interesting master's thesis produced from the work of the group missing from the web page, which were now added:
  • Ville Korhonen:
    Portable OpenCL Out-of-Order Execution Framework for Heterogeneous Platforms (December, 2014) (link)
  • Henry Linjamäki:
    Instruction Memory Hierarchy Generation for Customized Processors (2015) (link)
  • Aleksi Tervo:
    Optimizing Transport-Triggered Architectures for Field-Programmable Gate Arrays (2018) (link)

October 7th, 2019: New publications added

  • Kanishkan Vadivel, Pekka Jääskeläinen, Roel Jordans, Heikki Kultala, Sander Stuijk, Henk Corporaal:
    "Towards Efficient Code Generation for Exposed Datapath Architectures",
    in SCOPES 2019: 22nd International Workshop on Software and Compilers for Embedded Systems (Sankt Goar, Germany, May, 2019) (download).
  • Sven Gesper, Moritz Weißbrich, Stephan Nolting, Tobias Stuckenberg, Holger Blume, Guillermo Payá Vayá, Pekka Jääskeläinen:
    "Evaluation of Different Processor Architecture Organizations for On-Site Electronics in Harsh Environments",
    in SAMOS XIX: Embedded Computer Systems: Architectures, MOdeling, and Simulation (Samos, Greece, July 2019) (download).
  • Joonas Multanen, Pekka Jääskeläinen, Asif Ali Khan, Fazal Hameed, Jeronimo Gastrillon:
    "SHRIMP: Efficient Instruction Delivery with Domain Wall Memory",
    in ACM/IEEE International Symposium on Low Power Electronics and Design (Lausanne, Switzerland, July 2019) (download).
  • Alex Hirvonen, Kati Tervo, Heikki Kultala, Pekka Jääskeläinen:
    "AEx: Automated Customization of Exposed Datapath Soft-Cores",
    in Euromicro Conference on Digital System Design (Kallithea, Greece, August 2019) (download).
  • Jakub Zadnik, Jarmo Takala:
    "Low-power Programmable Processor for Fast Fourier Transform Based on Transport Triggered Architecture",
    in 2019 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP) (download).

May 2nd, 2019: New publications added

LordCore, a FP16 SIMD multicore TTA co-design case study we did in the ALMARVI project is now finally published as an article:
  • Heikki Kultala, Timo Viitanen, Heikki Berg, Pekka Jääskeläinen, Joonas Multanen, Mikko Kokkonen, Kalle Raiskila, Tommi Zetterman, Jarmo Takala:
    "LordCore: Energy-Efficient OpenCL-Programmable Software-Defined Radio Coprocessor",
    in IEEE Transactions on Very Large Scale Integration (VLSI) Systems (Volume 27, Issue 5, May 2019) (download).
Also added a Polar Decoder case study published by our colleagues in Bordeaux:
  • Mathieu Léonardon, Camille Leroux, Pekka Jääskeläinen, Christophe Jego, Yvon Savaria:
    "Transport Triggered Polar Decoders",
    in 2018 IEEE 10th International Symposium on Turbo Codes & Iterative Information Processing (ISTC) (download).
Please let us know if you have a TTA/TCE-related publication to add to the list!

January 10th, 2019: New publications added

Two conference publications we published during Fall time:
  • Joonas Multanen, Heikki Kultala, Pekka Jääskeläinen, Timo Viitanen, Aleksi Tervo, Jarmo Takala:
    "LoTTA: Energy-Efficient Processor for Always-On Applications",
    in SiPS 2018: IEEE Workshop on Signal Processing Systems (Cape Town, South Africa, October 2018) (download).
  • Joonas Multanen, Heikki Kultala, Pekka Jääskeläinen:
    "Energy-Delay Trade-Offs in Instruction Register File Design",
    in IEEE Nordic Circuits and Systems Conference (Tallinn, Estonia, October 2018) (download).
  • Mathieu Léonardon, Camille Leroux, Pekka Jääskeläinen, Christophe Jego and Yvon Savaria:
    "Transport Triggered Polar Decoders",
    in The 10th International Symposium on Turbo Codes & Iterative Information Processing (Hong Kong, China, December 2018) (download).

October 19th, 2018: New publications added

These workshop and conference publications we published during Spring and Summer time and can be now found in proceedings:
  • Jos IJzerman, Timo Viitanen, Pekka Jääskeläinen, Heikki Kultala, Lasse Lehtonen, Maurice Peemen, Henk Corporaal, Jarmo Takala:
    "AivoTTA: An Energy Efficient Programmable Accelerator for CNN-Based Object Recognition",
    in SAMOS XVIII: Embedded Computer Systems: Architectures, MOdeling, and Simulation (Samos, Greece, July 2018) (download).
  • Pekka Jääskeläinen, John Glossner, Martin Jambor, Aleksi Tervo, Matti Rintala:
    "Offloading C++17 Parallel STL on System Shared Virtual Memory Platforms",
    in 3rd Workshop on Open Source Supercomputing (OpenSuco3 within ISC 2018, June, Frankfurt, Germany) (download).
  • Jääskeläinen, P., Tervo, A., Paya-Vaya, G., Viitanen, T., Behmann, N., Takala, J., & Blume, H. (2018).:
    "Transport-Triggered Soft Cores",
    in 2018 IEEE International Parallel and Distributed Processing Symposium, Workshops (IPDPSW) (download).

July 11th, 2018: New publications and a Twitter account added

A couple of new publications were added:

  • Timo Viitanen, Janne Helkala, Heikki Kultala, Pekka Jääskeläinen, Jarmo Takala, Tommi Zetterman, Heikki Berg:
    "Variable Length Instruction Compression on Transport Triggered Architectures",
    in International Journal of Parallel Programming, 2018 (download).
  • Multanen, J., Viitanen, T., Jääskeläinen, P. & Takala, J.:
    "Instruction Fetch Energy Reduction with Biased SRAMs",
    in Journal of Signal Processing Systems, 2018 (download).
  • Heikki Kultala, Pekka Jääskeläinen, Johannes Ijzerman, Timo Viitanen, Markku Mäkitalo, Jarmo Takala:
    "Exposed Datapath Optimizations for Loop Scheduling",
    in SAMOS XVII: Embedded Computer Systems: Architectures, MOdeling, and Simulation (Samos, Greece, July 2017) (download).
  • Mona Aghababaeetafreshi, Matias Koskela, Dani Korpi, Pekka Jääskeläinen, Mikko Valkama, Jarmo Takala:
    "Software Defined Radio Implementation of Adaptive Nonlinear Digital Self-interference Cancellation for Mobile Inband Full-Duplex Audio",
    in GlobalSIP: 4th IEEE Global Conference on Signal & Information Processing (Washington D.C., USA, December 2016) (download).

CPC also now has a Twitter account where we plan to announce new publications and other activities.

May 17th, 2017: New publications added

  • Jukka Teittinen, Markus Hiienkari, Indrė Žliobaitėb, Jaakko Hollmen, Heikki Berg, Juha Heiskala, Timo Viitanen, Jesse Simonsson, Lauri Koskinen:
    "A 5.3 pJ/op approximate TTA VLIW tailored for machine learning",
    in Microelectronics Journal, Volume 61, March 2017 (download).
  • Pekka Jääskeläinen, Timo Viitanen, Jarmo Takala, Heikki Berg:
    "HW/SW Co-design Toolset for Customization of Exposed Datapath Processors",
    in Computing Platforms for Software-Defined Radio (book chapter pp 147-164), December 2016 (download).
  • Joonas Multanen, Timo Viitanen, Pekka Jääskeläinen, Jarmo Takala:
    "Xor-Masking: a Low-Overhead Method for Instruction Fetch Energy Reduction with Emerging SRAM Technologies",
    in SiPS 2016: IEEE Workshop on Signal Processing Systems (Dallas, Texas, October 2016) (download).
  • Joonas Multanen, Heikki Kultala, Matias Koskela, Timo Viitanen, Pekka Jääskeläinen, Jarmo Takala, Karen Egiazarian, Aram Danielyan, Cristóvão Cruz:
    "OpenCL Programmable Exposed Datapath High Performance Low-Power Computational Imaging Accelerator",
    in IEEE Nordic Circuits and Systems Conference (Copenhagen, Denmark, November 2016) (download).
  • Heikki Kultala, Timo Viitanen, Pekka Jääskeläinen, Jarmo Takala:
    "Aggressively Bypassing List Scheduler for Transport Triggered architectures",
    in SAMOS XVI: Embedded Computer Systems: Architectures, MOdeling, and Simulation (Samos, Greece, July 2016) (download).
  • N.Behmann, C. Seifert, G. Paya-Vaya, H. Blume, P. Jääskeläinen, J.Multanen, H. Kultala, J. Takala, J. Thiemann, S. van de Par:
    "Customized High Performance Low Power Processor for Binaural Speaker Localization",
    in IEEE Int'l Conference on Electronics, Circuits, & Systems (Monte Carlo, Monaco, December 2016) (download).
TCE-related news here