Course Catalog 2008-2009 Basic Basic Pori International Postgraduate Open University |Degrees|     |Study blocks|     |Courses|

Course´s person responsible

Olli Vainio

Implementations

	Lecture times and places	Target group recommended to
Implementation 1

Requirements

Exam

Principles and baselines related to teaching and learning

-

Objectives

To learn design for testability for digital circuits and systems-on-chip.

Content

Content	Core content	Complementary knowledge	Specialist knowledge
1.	Fault models in digital circuits. Fault detection.	Fault models for memories.	Shared use of package pins.
2.	Scan architecture and its use for testing.	Test development using Boolean algebra.	Special clocking arrangements.
3.	Built-in self test.	ATPG principles.	ATPG design rules.
4.	Testing memories and processor cores.	Features of core processors.	MBIST integration.
5.	Terminology of the field.	The test wrapper.	Wrapper-originating requirements for DFT.

Study material

Type	Name	Author	ISBN	URL	Edition, availability, ...	Examination material	Language
Book	Design for Test for Digital IC	A. L. Crouch	0-13-084827-1				English
Book	Fault Tolerant & Fault Testable Hardware Design	Parag K. Lala	0-13-308248-2				English

Prerequisites

Correspondence of content

Additional information

The course is given only every other year.

More precise information per implementation

	Description	Methods of instruction	Implementation
Implementation 1		Lectures Practical works	Contact teaching: 0 % Distance learning: 0 % Self-directed learning: 0 %

Last modified	22.08.2008
Modifier	Johanna Reponen