Courses persons responsible
Claudio Brunelli

Lecturers
Claudio Brunelli

Language of Instruction
The course is lectured in English

Implementations

Person responsible:

Jari Nurmi

	Period 1	Period 2	Period 3	Period 4	Period 5	Summer
Lecture	-	-	-	2 h/week	2 h/week	-
Exercise	-	-	-	1 h/week	1 h/week	-
Exam

(Timetable for academic year 2006-2007)

Objectives
Providing knowledge about computers and microprocessor-based systems, and specially parallel architectures.

Content

Content	Core content	Complementary knowledge	Specialist knowledge
1.	Media processors and support for multimedia in processor instruction set
2.	Dynamic usage of parallelism, Tomasulo scheme algorithm, branch prediction, conditional execution. Instruction-level parallelism and its limitations.	Superscalar processors and speculative execution. Extraction of parallelism in programs.
3.	VLIW and EPIC architectures and their compiler support. Static and dynamic compilation techniques.Parallelism in embedded systems.
4.	Enhancing cache memory performance. Parallel memory architectures.	Memory hierarchy design.
5.	Multi-processor systems and thread-level parallelism. Processors and processes synchronization and communication. Interconnections and clustering.	Performance analysis of I/O systems. Mutli-processor cache-concurrency.

Requirements for completing the course
Exercises, exam

Evaluation criteria for the course

Study material

Type	Name	Auhor	ISBN	URL	Edition, availability...	Exam material	Language
Book	Computer architecture: a quantitative approach	Hennessy, Pattersson			3rd and 4th	No	English

Prerequisites

Code	Course	Credits	M/R
TKT-3206	TKT-3206 Computer Architecture I	5	Mandatory

Prequisite relations (Sign up to TUT Intranet required)

Remarks

Scaling

Methods of instruction	Hours
Lectures	60
Exercises	48

Other scaled	Hours
Preparation for exam	20
Exam/midterm exam	3
Total sum	131

Course homepage

Last modified	26.04.2007
Modified by	Jari Nurmi