Courses persons responsible
Olli Vainio

Lecturers
Olli Vainio

Language of Instruction
Lectured in Finnish or English according to demand.

Implementations

Person responsible:

Olli Vainio

	Period 1	Period 2	Period 3	Period 4	Period 5	Summer
Lecture	2 h/week	2 h/week	-	-	-	-
Exercise	2 h/week	2 h/week	-	-	-	-
Exam

(Timetable for academic year 2006-2007)

Objectives
To learn methods for modelling and designing asynchronous digital circuits.

Content

Content	Core content	Complementary knowledge	Specialist knowledge
1.	Asynchronous protocols.	VHDL modeling of asynchronous circuits.	Product examples.
2.	Graphical representations.	Applications.
3.	Huffman and Muller circuits.	Timed circuits.
4.		Verification.

Requirements for completing the course
Exam and compulsory exercise projects.

Evaluation criteria for the course

Study material

Type	Name	Auhor	ISBN	URL	Edition, availability...	Exam material	Language
Book	Asynchronous Circuit Design	Chris J. Myers	0-471-41543-X	http://www.async.elen.utah.edu/book/		Yes	English

Prerequisites

Code	Course	Credits	M/R
MAT-20600	MAT-20600 Discrete Mathematics	3	Mandatory
TKT-1200	TKT-1200 Digital Design I	4	Mandatory
TKT-1210	TKT-1210 Digital Design II	5	Mandatory

Prequisite relations (Sign up to TUT Intranet required)

Additional information about prerequisites
Basics of discrete mathematics, digital design and VHDL are required as prerequisites.

Remarks

Distance learning

- In information distribution via homepage, newsgroups or mailing lists, e.g. current issues, timetables
- In compiling exercise, group or laboratory work

- Contact teaching: 36 %
- Distance learning: 0 %
- Proportion of a student's independent study: 64 %

Scaling

Methods of instruction	Hours
Lectures	36
Exercises	36
Assignments	15

Study materials	Hours
Book	40
Total sum	127

Correspondence of content
TKT-1530 Asynchronous Circuits

Course homepage

Last modified	20.04.2006
Modified by	Olli Vainio