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TKT-1506 ASIC DESIGN II, 5 cr
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Courses persons responsible
Olli Vainio
Lecturers
N.N.
Implementations
| Period 1 | Period 2 | Period 3 | Period 4 | Period 5 | Summer | |
| Lecture | - | - | - | 2 h/week | 2 h/week | - |
| Exercise | - | - | - | 1 h/week | 1 h/week | - |
| Exam | ||||||
Objectives
To learn post-synthesis (backend) design of ASICs.
Content
| Content | Core content | Complementary knowledge | Specialist knowledge |
| 1. | Transistors, wires, and parasitic components in ICs. | ||
| 2. | Floorplanning, clock tree generation, supply wiring, and the nonidealities therein. | ||
| 3. | Placement and routing of standard cells, netlist extraction, backannotation. | ||
| 4. | Cell design and optimization, timing issues, memory cell design. | ||
| 5. | Large system chips. Testability. |
Requirements for completing the course
Exam and compulsory exercise work.
Evaluation criteria for the course
Study material
| Type | Name | Auhor | ISBN | URL | Edition, availability... | Exam material | Language |
| Book | Digital Integrated Circuits: A Design Perspective | J.M. Rabaey, A. Chandrakasan, B. Nicolic | 0-13-120764-4 | 2nd edition | Yes | English |
Prerequisites
| Code | Course | Credits | M/R |
| TKT-1216 | TKT-1216 Digital Design II | 5 | Recommendable |
| TKT-1236 | TKT-1236 Digital Systems Laboratory | 3 | Recommendable |
| TKT-1400 | TKT-1400 ASIC Design I | 5 | Recommendable |
Prequisite relations (Sign up to TUT Intranet required)
Remarks
Distance learning
- In information distribution via homepage, newsgroups or mailing lists, e.g. current issues, timetables
Scaling
| Methods of instruction | Hours |
| Lectures | 48 |
| Exercises | 36 |
| Assignments | 16 |
| Study materials | Hours |
| Book | 30 |
| Other scaled | Hours |
| Exam/midterm exam | 3 |
| Total sum | 133 |
| Last modified | 20.04.2006 |
| Modified by | Olli Vainio |